AMD: ZEN3 architecture finished – expects 15% faster IPC
AMD’s earlier this week hosted a presentation at the SC19 conference, an International Conference for High-Performance Computing, Networking, Storage, and Analysis. AMD made some interesting remarks about ZEN3 and Epyc in regards to development as well as IPC increases.
First off, AMD mentions the ZEN3 architecture design phase has been finished. Nowadays you can look at AMDs design and release phases as the traditional tick-tock release schedule. Here you may expect an iterated update of ZEN2. That’s said, ZEN3 should be seen as a new architecture is mentioned, which is interesting. We know that ZEN3 is a 7nm+ based product based on the below roadmap slide that was shared a while ago.
Zen1 compared to Zen2 brought a clock-for clock IPC increase of 21%, AMD says it careful, but hints at yet another 15% IPC increase for ZEN3, that’s again clock for clock and not counting faster clock frequencies. The necessity of more cores has not ended, and the future design path will be based on more cores and a greater compute density as well as a focus on memory bandwidth and I/O connectivity.
AMD qualified the remarks by pointing out that Zen 2 delivered a bigger IPC gain than what's normal for an evolutionary upgrade - AMD has said it's about 15% on average - since it implemented some ideas that AMD originally had for Zen but had to leave on the cutting board. However, he also asserted that Zen 3 will deliver performance gains "right in line with what you would expect from an entirely new architecture."
Despite earlier rumors, AMD also confirmed that ZEN3 and Epyc CPUs will not use a maximum of four threads per core, so you can 'bin' that idea. On the Epyc side, there was news as well, Amazon will be deploying Epyc 2 technology for their server farms and thus web services servers, which is huge for AMD of course. 64-core Rome processors will also be used in Microsoft's Azure service.
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If it's the same socket would previous gen Ryzen work with ddr5 and wouldn't that increase bandwidth for the bandwidth sensitive early Ryzens or is the cpu limited to ddr4 in hardware
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They’ve redesigned the architecture for Zen 3. The cache will be very different and not have latency issues like Zen 2 because of CCX. The cache will be shared by all cores, so it won’t matter if Windows makes a single thread jump from core to core all over the CPU.
There might even be a L4 cache.
Lets hope they will lower the Latency and fix Core Scheduling performance loss which is present in Zen 2. CCX , because Windows can't use the cores to their max. potential with Zen 2 CPU's. Agree that big part of the improvements in IPC will come from the cache memory shared by all cores in Zen 3 for sure.
First we fix the CCX design errors from Zen 2 in Zen 3 ,after we speak about the 15 % improvements in IPC in Zen 3, clear win win situation
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I just wish they'd build a decent CPU/APU for laptops that doesn't hog battery like current ones do.
Intel basically has 100% of the laptop market (which is not a small market at all) and even nowadays it's still difficult to recommend anything with an AMD CPU/APU.
As for their desktop CPUs, I'm impressed by Zen 2/3... but if I had to buy anything, I'd probably wait for Zen 4, which will have 3 or 4 threads per core, and will probably bring DDR5 (couldn't care less about PCI-Express 5.0 though). If Zen 3 delivers, surely Zen 4 will be a complete beast.
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There's always going to be a latency penalty communicating BEWTWEEN CCX's. This is an inherent limitation of the design. You can some what mitigate via the evils such as branch prediction, you will not eliminate it.
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Even if it is only 10% that'll be enough i feel to overtake Intel as the number one CPUs for gaming.
Intel is still the leader in gaming by only a few percentage now, so any IPC increase by AMD will be a win win for AMD and us.
I think it'll still be AM4 socket but a new chipset may be released 670X maybe.