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AMD ZEN2 Rome Listed in Sandra, shows doubled up L3 caches
We've been going back and forth on AMD's 7nm ZEN. We've seen the announcements and the hype is real for 2019 when the first products will be released. The first series, of course, will be for Epyc, the server products, with up to 64-cores I might add. In the SiSoft Sandra Database, a first entry has been found and is showing interesting stuff.
The part listed is ROME (actually it is a server with two of these puppies (that's 128 cores / 256 threads)) and was spotted and posted at reddit. Anyway, ROme is the 64-core part. Here's the interesting part, the database entry shows a setup based on 512 KB dedicated L2 cache per core, and then 16x 16 MB L3. So each CPU block is tied to 16 MB L3. Sixteen L3 partitions indicate 4 cores per chiplet (4x16=64 cores). For example, the Ryzen 7 2700X the L3 cache is arranged as "2x 8 MB L3," here each CCX holding four cores has an L3 cache amount of 8 MB. All things considered, we cannot 100% trust a SiSoft Sandra early listing though. But if true, it's pretty huge progression.
These processors are of course data-center products, but you know it, this architecture always end up in desktop processors. A number of announcements have been made, yes Zen2 is based on 7nm, yes AMD has working samples and yes they will arrive in 2019. So far all it pretty interesting. AMD expects a 25% generational performance increase for the CPU cores. While that's not IPC, the theory is that one die package would be 25% faster.
ZEN2 is not just a die-shink, it's new architecture and the rumor from a while ago was true, it's based on chipsets. 7nm dies surrounding one 14nm IO chip in the center connected through AMD's Infinity fabric. The "Zen 2" high-performance x86 CPU processor core thus has a modular design methodology. An improved AMD Infinity Fabric interconnect links the separated pieces of silicon ("chiplets") within a single processor package. So that is why you see nine dies.
This should solve some latency issues. The new processor also will support 8-channel DDR4 memory. Also, PCI-Express will be supported. Rome looks amazing, the dies are just so small.
Second-generation AMD ZEN2 To launch Next year on 7nm - 05/02/2018 08:16 AM
In a Q1 2018 Earnings, Call Transcript AMD CEO Lisa T. Su was interviewed, she dropped a few interesting notes. AMD is hard at work on 7nm parts, the first products will sample this year already, wi...
New Leak reveals AMD Zen2 and Zen3 codenames and adds a Timeline - 03/08/2018 08:26 AM
Yet another leak, this time it's not so much the intricate technology specifications, but rather a roadmap and timeline, showing not just the codenames of upcoming Zen2 but also Zen3. Looks like AMD...
asturur
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#5610742 Posted on: 11/26/2018 10:29 AM
oh do you think all the cache is there?
oh do you think all the cache is there?
Fox2232
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#5610745 Posted on: 11/26/2018 10:33 AM
It is L3. That definitely does not need to be locally present in chiplets. L1 must be inside CPU chiplet. L2 is likely better off in CPU chiplet too. But L3, maybe having it in big Chip may allow for some extra optimizations.
oh do you think all the cache is there?
It is L3. That definitely does not need to be locally present in chiplets. L1 must be inside CPU chiplet. L2 is likely better off in CPU chiplet too. But L3, maybe having it in big Chip may allow for some extra optimizations.
asturur
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#5610754 Posted on: 11/26/2018 11:40 AM
well if the infinity fabric is used to fetch from l3 to l2 and that IO thing fetch from memory to l3, i can see how you should not have efficency hit.
Also use the 7 nanometers process to do cores and not memory.
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Is just a curiosity because we know this change is out of scope for various reasons. I m just wondering if it would be techincally possible
well if the infinity fabric is used to fetch from l3 to l2 and that IO thing fetch from memory to l3, i can see how you should not have efficency hit.
Also use the 7 nanometers process to do cores and not memory.
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Is just a curiosity because we know this change is out of scope for various reasons. I m just wondering if it would be techincally possible
nevcairiel
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#5610758 Posted on: 11/26/2018 12:02 PM
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Well, you have to change the motherboard, thats no question. Every memory channel is connected to the CPU, while slots on the same channel are connected differently. The real question is if they can do it without a new socket - and that depends if it was pre-planned and/or enough reserved pins are available.
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Well, you have to change the motherboard, thats no question. Every memory channel is connected to the CPU, while slots on the same channel are connected differently. The real question is if they can do it without a new socket - and that depends if it was pre-planned and/or enough reserved pins are available.
Aura89
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#5610760 Posted on: 11/26/2018 12:22 PM
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Well, you have to change the motherboard, thats no question. Every memory channel is connected to the CPU, while slots on the same channel are connected differently. The real question is if they can do it without a new socket - and that depends if it was pre-planned and/or enough reserved pins are available.
This news item is for servers, of which states 8-channel support, of which current 1st gen Epyc processors already support 8-channel memory.
If this goes over to threadripper as 8-channel capable, we'll see, but i doubt it, there's not a huge reason to. But considering Epyc and Threadripper use effectively the same socket/pins, there's also likely nothing "stopping" them from supporting it if they wanted.
But i very much doubt that 8-channel is coming to threadripper, or 4-channel is going to Ryzen.
On a separate topic i wonder if they can transition to more memory channel without changing them motherboard, assuming the controller for memory is in the package and not in the MB this could be eventually possible.
Well, you have to change the motherboard, thats no question. Every memory channel is connected to the CPU, while slots on the same channel are connected differently. The real question is if they can do it without a new socket - and that depends if it was pre-planned and/or enough reserved pins are available.
This news item is for servers, of which states 8-channel support, of which current 1st gen Epyc processors already support 8-channel memory.
If this goes over to threadripper as 8-channel capable, we'll see, but i doubt it, there's not a huge reason to. But considering Epyc and Threadripper use effectively the same socket/pins, there's also likely nothing "stopping" them from supporting it if they wanted.
But i very much doubt that 8-channel is coming to threadripper, or 4-channel is going to Ryzen.
Astyanax
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#5610769 Posted on: 11/26/2018 01:09 PM
There is, the fact the x399 socket is wired to have 8 dimms connected to 4 controllers instead of 8 dimms wired to 8 controllers.
There is, the fact the x399 socket is wired to have 8 dimms connected to 4 controllers instead of 8 dimms wired to 8 controllers.
Aura89
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#5610772 Posted on: 11/26/2018 01:16 PM
Redundancies in systems that would allow a CPU to work in 8-channel or 4-channel based off the motherboard chipset it is in considering that socket is used for both 4-channel and 8-channel is information we do not know about.
I didn't say it wouldn't require a new motherboard chipset, obviously if they brought 8-channel memory support to threadripper, it would be via a different chipset, but that doesn't mean it wouldn't still be backwards compatible with previous chipsets for 4-channel.
But again, i do not believe that will happen. I see no reason as to why they would change from Ryzen being dual, Threadripper being quad, and Epyc being 8-channel.
There is, the fact the x399 socket is wired to have 8 dimms connected to 4 controllers instead of 8 dimms wired to 8 controllers.
Redundancies in systems that would allow a CPU to work in 8-channel or 4-channel based off the motherboard chipset it is in considering that socket is used for both 4-channel and 8-channel is information we do not know about.
I didn't say it wouldn't require a new motherboard chipset, obviously if they brought 8-channel memory support to threadripper, it would be via a different chipset, but that doesn't mean it wouldn't still be backwards compatible with previous chipsets for 4-channel.
But again, i do not believe that will happen. I see no reason as to why they would change from Ryzen being dual, Threadripper being quad, and Epyc being 8-channel.
AlmondMan
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#5610789 Posted on: 11/26/2018 02:29 PM
Double up on cache, double up on cores? Seems they found a way to glue CCXs together too!
Double up on cache, double up on cores? Seems they found a way to glue CCXs together too!
asturur
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#5610797 Posted on: 11/26/2018 03:03 PM
This i did not know.
I thought that since the memory controller is moved in the cpu, each dimm socket would go to the cpu and that the 2/4 channel would have been something internal wiring to the memory controller. ( the mb chipset do not play a role in the configuration, i m sure )
It was a generic question not related to ryzen or threadripper or Epyc in particular.
Well, you have to change the motherboard, thats no question. Every memory channel is connected to the CPU, while slots on the same channel are connected differently
This i did not know.
I thought that since the memory controller is moved in the cpu, each dimm socket would go to the cpu and that the 2/4 channel would have been something internal wiring to the memory controller. ( the mb chipset do not play a role in the configuration, i m sure )
It was a generic question not related to ryzen or threadripper or Epyc in particular.
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#5610802 Posted on: 11/26/2018 03:13 PM
Did you mean chiplets?
'member when L2 caches used to be wholly separate from the CPU package?
ZEN2 is not just a die-shink, it's new architecture and the rumor from a while ago was true, it's based on chipsets
Did you mean chiplets?
It is L3. That definitely does not need to be locally present in chiplets. L1 must be inside CPU chiplet. L2 is likely better off in CPU chiplet too. But L3, maybe having it in big Chip may allow for some extra optimizations.
'member when L2 caches used to be wholly separate from the CPU package?
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#5610838 Posted on: 11/26/2018 04:48 PM
I cant wait to see Zen 2 official review.
Will be intresting how much cores new top model will have.
12 core 3700X can be alright.
I cant wait to see Zen 2 official review.
Will be intresting how much cores new top model will have.
12 core 3700X can be alright.
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#5610874 Posted on: 11/26/2018 06:35 PM
'member when L2 caches used to be wholly separate from the CPU package?
I 'member that!
'member when L2 caches used to be wholly separate from the CPU package?
I 'member that!
Alessio1989
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#5610890 Posted on: 11/26/2018 07:22 PM
Zen 2 threads are becoming an hard-porn video collections.
Zen 2 threads are becoming an hard-porn video collections.
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#5610917 Posted on: 11/26/2018 08:51 PM
I've heard speculation that the cache in the IO die might contain a copy of the cache for each chiplet, which would negate the need for chiplet-to-chiplet communication.
It is L3. That definitely does not need to be locally present in chiplets. L1 must be inside CPU chiplet. L2 is likely better off in CPU chiplet too. But L3, maybe having it in big Chip may allow for some extra optimizations.
I've heard speculation that the cache in the IO die might contain a copy of the cache for each chiplet, which would negate the need for chiplet-to-chiplet communication.
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Maybe that can explain hugeness of that central die.