AMD Zen will get 8 channel DDR4 support and SMT says CERN employee

An interesting snippet of news just before the weekend starts, AMD ZEN based processors will get up-to 8 channels of DDR4 support as well as SMT. The info was spilled by CERN engineer Liviu Valsan who in a recent presentation on datacenter hardware trends shared a thing or two about AMD's upcoming Zen processor architecture. 

According to a slide from Liviu the upcoming x86 processors based on Zen will feature of up to 32 physical cores, however Valsan stated AMD will use two 16-core CPUs on a single die, so that's a bit of an old trick really. But it does confirm earlier findings. It however immediately places the 8 memory channels in debate, as you might look at it as two quad channel setups then.
  

Processor cores wise initially far more realistic would be four, eight and perhaps in the no too distant future 16 cores. Interesting is the mention of an SMT design. AMD already slightly hinted towards it, now it is confirmed. SMT means symmetrical multi-threading and it would be the equivalent to Intel's Hyper-threading. The Zen architecture will be built on a more efficient 14 nanometer FinFET process, rather than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.

The Zen family processors for consumers will feature a unified AM4 socket with its GPU-equipped "Bristol Ridge" APU counterparts, and feature DDR4 support and a 95W TDP.  While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15W and 15 to 35W for performance-oriented mobile products with up to four Zen cores.

Each Zen core will have four integer units, two address generation units and four floating point units, and the decoder can decode four instructions per clock cycle. L1 data cache size is 32 KiB and L2 cache size 512 KiB per core. Two of the floating point units are adders, two are multipliers.
 

The completely new design will be 40% faster per core / instruction / clock cycle compared to the current Excavator cores, and that would be a serious increase alright. The throughput should increase significantly thanks to Simultaneous Multithreading, so yeah all things considered, this is looking good and sound with this architecture.