AMD Zen Summit Ridge Die says Hello
Over at SemiAccurate they spotted something interesting, it seems to be the AMD Zen Summit Ridge Die as AMD seems to have accidentally outed a rendering of the wafer at its May 12th shareholders meeting.
Summit Ridge is the high-end desktop (HEDT) product that AMD has previously promised to release in Q4 of this year. It’s expected to be the first chip that integrates AMD upcoming Zen CPU architecture. Expectations are high and Summit Ridge may prove to be a make or break product for AMD.
The "Summit Ridge" Zen family will feature a unified AM4 socket with its GPU-equipped "Bristol Ridge" APU counterparts, and feature DDR4 support and a 95W TDP. While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15W and 15 to 35W for performance-oriented mobile products with up to four Zen cores.
Each Zen core will have four integer units, two address generation units and four floating point units, and the decoder can decode four instructions per clock cycle. L1 data cache size is 32 KiB and L2 cache size 512 KiB per core. Two of the floating point units are adders, two are multipliers.
See the wafer shot below ...
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Senior Member
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Could be a potential beast after all..
Well 16threads sounds good, and if its 1.6x AMD FX single core perf. then it could be faster then Haswell/Skylake too.

sause: well not so good but still somethin

it’s important to remember that AMD’s latest Orochi dies feature Piledriver cores rather than Excavator. Excavator cores are roughly 15% faster per clock than Piledriver This in turn puts Zen at a lead in excess of 60% vs Piledriver in terms of performance per clock. Doubling the performance of the FX 8350 puts Zen in direct competition with Intel’s eight core i7 5960X.
Junior Member
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The article says the front end can decode 4 ops/cycle, which may not be true.
Each of the four decoders can decode FastPath, which decodes into multiple ops. Most likely the average will be ~6 ops/cycle unless the decoders can only operate every other cycle.
It is quite likely that the connections to the decoders can only handle 6 ops/cycle - even if the decoders could actually decode 8~12 ops/cycle (absolute peak).
Senior Member
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Poor AMD. They don't know, that Jim Keller sold them their old architecture

Anyway, it's interesting to compare Pentium III and Core Architectures.


Well , Phenom (k10) was competitive only with Core arhitecture, Nehalem just got too faster . Bulldozer was barely able to compete with Nehalem ,not to mention Sandybridge . So , yes , I expect Zen to be somewhere between Sandybridge and Haswell , at most....
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Between Sandybridge and Haswell is Ivy Bridge. Considering Skylake is amazing 10% faster than Ivy Bridge (I'd know since I just upgraded from Ivy to Sky), it would place Zen right next to Skylake's performance, especially assuming it overclocks as well as Intel CPUs so that a simple OC wouldn't allow Intel to beat it again. Coupled with double the amount of physical cores, it would be jolly good.
Senior Member
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According to the slide, Summit ridge will have up to 8 "cores"
And according to Guru3d, which says each core will have 4 integer units and 4 FP units.. it looks like we could have up to 32 threads on one CPU.
That would be sweet!