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AMD Zen 4 Die Cache Sizes, Latencies And Transistor Counts Detailed
Chiakokhua (aka Retired Engineer) posted a table comparing the latencies of the various caches to those of the "Zen 3" core. AMD's Mark Papermaster announced at the Ryzen 7000 launch event that the company has increased the core's micro-op cache from 4 K entries to 6.75 K entries.
The L1I and L1D caches remain 32 KB each, whereas the L2 cache has more than doubled in size. The expansion of the L2 cache increased latency somewhat, from 12 to 14. The shared L3 cache's latency has also increased, from 46 to 50 cycles. The dispatch stage's reorder buffer (ROB) has been increased from 256 to 320 entries. The size of the L1 branch target buffer (BTB) has been raised from 1 KB to 1.5 KB. Because of the transition to 5 nm, the Zen 4 CCD is slightly smaller than the Zen 3 CCD despite having more transistors (TSMC N5 process). The CCD is 70 mm2 in size, unlike the 83 mm2 Zen 3"CCD. The "Zen 4" CCD has 6.57 billion transistors, a 58 percent increase over the "Zen 3" CCD's 4.15 billion transistors.The cIOD (client I/O die) is seeing a lot of innovation. It's manufactured on the 6 nm (TSMC N6) node, which is a significant improvement over the GlobalFoundries 12 nm node used for the cIOD of Ryzen 5000 series processors. Certain power-management capabilities from the Ryzen 6000 "Rembrandt" processors are also included. Aside from DDR5 memory controllers and a PCI-Express Gen 5 root complex, this cIOD includes an iGPU based on the RDNA2 graphics architecture. The new 6 nm cIOD measures 124.7 mm2, which is somewhat larger than the Ryzen 5000 series' 124.9 mm2 cIOD.
The multi-chip module Raphael contains one CCD for the 6-core and 8-core SKUs and two CCDs for the 12-core and 16-core SKUs. The Socket AM5 package is used to build "Raphael." AMD is said to be working on a small BGA packaging of "Raphael" for high-performance notebook platforms, dubbed "Dragon Range." These CPUs will be available in 45 W, 55 W, and 65 W TDP configurations, and will power high-end gaming notebooks.
Cinebench R20 Score for AMD Zen 4 Ryzen 7 7700X Processor Leaked - 08/25/2022 09:16 AM
Extreme Player, a tech news publication on Bili Bili, apparently leaked the Cinebench R20 score of an AMD Ryzen 7 7700X Zen 4 processor (probably engineering sample)....
AMD Zen 4 EPYC CPU Benchmarked - 17% Single Thread Performance Increase (192-core, 384-thread) - 08/23/2022 08:55 AM
An EPYC 9664 appears on Geekbench 5 in a dual-socket configuration for a total of 192 cores and 384 threads. Performance places the processor approximately 17% ahead of an equivalently clocked 128 cor...
AMD Zen 4 CPU with 5.2 GHz Boost and RDNA 2 iGPU surfaces - 05/13/2022 09:17 AM
AMD's upcoming Ryzen 7000 (Raphael) processor is exposed. On Twitter Petykemano discovered the unknown 5nm chip in the OpenBenchmarking database....
AMD Zen 4 Based Genoa CPUs Get 1 MB L2 Cache per Core - 03/28/2022 03:47 PM
And that's a lot. In Geekbench some scores leaked, and while we don't trust geekbench scores, the specs however are listed in great detail. ...
AMD Zen 3 processors with 3D V-Cache in early 2022, then Zen 4 later that year with PCIe 5.0 and DDR5. - 10/12/2021 07:11 PM
It's been five years that the first Ryzen processors have been released. AMD posted an interview containing some nice details, AMD confirms that the first Zen 3 CPUs with stacked 3D V-Cache will be ...
umeng2002
Senior Member
Posts: 1316
Joined: 2006-09-02
Senior Member
Posts: 1316
Joined: 2006-09-02
#6046842 Posted on: 08/30/2022 11:45 PM
There is no way they would enable the iGPU if an I/O die was used as a Southbridge.
There is no way they would enable the iGPU if an I/O die was used as a Southbridge.
JamesSneed
Senior Member
Posts: 1677
Joined: 2017-02-14
Senior Member
Posts: 1677
Joined: 2017-02-14
#6046876 Posted on: 08/31/2022 02:58 AM
No its not this gen but I wouldn't doubt that comes in the future. AMD has said there will be no need for active cooling this generation.
Is the I/O chip still also used as a chipset? I hope this new boards don't need active cooling on the chipset
No its not this gen but I wouldn't doubt that comes in the future. AMD has said there will be no need for active cooling this generation.
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Strange that the L3 cache latency increased.
For the L2 is expected, as it doubled the size. But L3 is the same.
Could it have been adjusted for higher clock speeds of the Zen4?
given that they are pushing for 5.7ghz doesnt surprise me, unlike modern intel chips the cache frequency is locked with the cores on amd (dont think this has changed for zen4). reminds me of somethig i read a while back in the core 2 days, the legendary e0 stepping of the 45nm chips supposedly has looser cache timings and this allows those chips to hit ~4.5ghz+ where as the older c0 stepping gets stuck around 4.0-4.2ghz, but offers very slightly higher ipc.