AMD Zen 4 Based Genoa CPUs Get 1 MB L2 Cache per Core
And that's a lot. In Geekbench some scores leaked, and while we don't trust geekbench scores, the specs however are listed in great detail.
AMD Genoa ZEN4 based architecture will find its way into server and workstation CPUs, and thus specs are now leaked to some extent.
An engineering sample CPU is clocked at 1.2 GHz, not relevant since it's an ES sample, but noteworthy is that AMD has increased the L2 cache to 1 MB per core, that double the amount of its predecessor, which is a good thing.
This engineering sample does not appear to feature a 3D V-Cache. It has 128 MB of L3 cache. Even with the clock speed reduced, the Genoa CPU performs remarkably similarly to an EPYC 7513 in single core testing. The EPYC 7513 has a base speed of 2.6 GHz and a boost clock of 3.65 GHz, and it runs Ubuntu 20.04 LTS on both. It outperforms it on several of the subtests, such as navigation, SQLite, and HTML5. Speech recognition and rigid body physics are two areas where it gets close.
This is particularly remarkable given that the Genoa engineering sample operates at less than half the speed of the EPYC 7513. It is possible that it is working at a third of the normal speed. It is anticipated that AMD's Zen 4-based Genoa CPUs will be available later this year. In addition, models with up to 96 cores and 192 threads are envisaged, as well as 12-channel DDR5 memory and PCIe 5.0 expansion capabilities.
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This would confirm AM5 1MB L2 per core also right?
As far as I know cache is not something that previously has had yield problems, so there should not be any leftover desktop chips with half the cache blocked off, unless they are made on a different production line.
Yeah as long as AMD is keeping the chiplet designs the same which I have heard no reason why they wouldn't. Doubling the L2 is going to help with latency with the larger L3 caches since they have a little more latency so going there less often should help performance.
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Athlon Xp Barton introduced the 512KB L2 cache if i recall correctly, which also killed the P4's frequency lead.
Athlon 64 FX introduced 1MB L2 but also costed 1k euros...so idk if that was mainstream.
But those were in a time that L2 was the last level of cache( also process nodes were influencing cache latencies)
L2 size depends on latency penalty, ever since L3 cache became mainstream
Now L3 is the one that gets regular changes and its latency is not the most important metric, as we see with Zen
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What I really want to know is what are the planned 3D cache layouts for Zen 4! It is really between ADL, 5800X3D or Zen4 for gamers who want top performance now!
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If it helps boost performance/IPC (alongside that huge L3 cache) - then a win?
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You would want to compare that L2 to todays L2+L3 to be fair for a size comparison. Back in the day that was a pretty large L2 outside of some of the big iron like Sparc or Power chips.