Intel Core i9 9900KS processor review
AMD Ryzen 9 3950X review
Promo: Windows 10 Pro for $13 With Office 2016 For $33
ASUS PRIME X570 Pro review
ASUS ROG STRIX Scope keyboard review
GALAX GeForce RTX 2070 Super WTF review
ADATA Spectrix S40G 512GB NVMe M.2 SSD review
Red Dead Redemption 2: PC graphics performance benchmark review
XFX Radeon RX 5700 XT THICC III Ultra review
Promo: URcdkey Halloween sale Windows 10 Pro for 11$
AMD X590 Chipset Pops Up Again - 24 Full PCIe 4.0 lanes instead of 16?
In the past, we've mentioned an X590 chipset alongside the AMD X570 chipset. At the time I think AMD denied an X590 chipset, guess what? The name is now resurfacing. Short term you may expect the X570, B550 and A520 chipsets right?
Well, a while ago on 1Usmus's Twitter account (the tweet has since disappeared) a rumor was spread that the X590 chipset would arrive. And that now is becoming a little more credible in terms of information as an image has been published in a forum post , indicating that the X590 chipset is referred to in the bios of various X570 motherboards.
Computer base forum user CM87 noticed that in the official BIOS for X570 motherboards the X590 chipset is mentioned. If all this is true, we have no idea what the real differences could be. A new Threadripper chipset (if even released) would likely be named X599 right? There has been talk about the ASMedia PCH at PCIe 4.0, which could be the difference. But if that is all, it would not warrant a new chipset name IMHO. As you know, AMD uses the X570's design of the I/O dies of the Ryzen 3000 CPUs. There are a total of 24 PCIe 4.0 lanes on the processors, four of which are reserved for the interlink to the chipset. The X570 has 16 PCIe lanes plus four for the uplink to the processor. Perhaps the new X590 chipset has a full 24 PCIe lanes as that is the only tangible different I think of.
For the time being let's take this info with a pinch of salt.
DmitryKo
Senior Member
Posts: 248
Joined: 2011-08-08
Senior Member
Posts: 248
Joined: 2011-08-08
#5681234 Posted on: 06/16/2019 11:16 AM
There would be little benefit from the extra 8 PCIe lanes in the PCH, as all these 24 lanes would map to the same 4-lane CPU uplink.
Now if they could reconfigure the CPU NVMe x4 link to double as the downlink lanes to the chipset...
There would be little benefit from the extra 8 PCIe lanes in the PCH, as all these 24 lanes would map to the same 4-lane CPU uplink.
Now if they could reconfigure the CPU NVMe x4 link to double as the downlink lanes to the chipset...
Evildead666
Senior Member
Posts: 1237
Joined: 2003-09-14
Senior Member
Posts: 1237
Joined: 2003-09-14
#5681236 Posted on: 06/16/2019 11:20 AM
There would be little use for the extra 8 PCIe lanes in the chipset as they all go through the same 4-lane uplink to the CPU.
Now if they could reconfigure the x4 NVMe link in the CPU to double on the downlink lanes to the chipset...
Then again, it would basically have one M2 slot less than X570, but have a x8 link to the chipset..not sure if worthy of X590.
There must be more to this, maybe even E-ATX boards.
edit : Microsemi has a storage PCIe 4.0 switch available since last year, and PLDA might have one. Broadcom could have one too (PLX chips).
There would be little use for the extra 8 PCIe lanes in the chipset as they all go through the same 4-lane uplink to the CPU.
Now if they could reconfigure the x4 NVMe link in the CPU to double on the downlink lanes to the chipset...
Then again, it would basically have one M2 slot less than X570, but have a x8 link to the chipset..not sure if worthy of X590.
There must be more to this, maybe even E-ATX boards.
edit : Microsemi has a storage PCIe 4.0 switch available since last year, and PLDA might have one. Broadcom could have one too (PLX chips).
HWgeek
Senior Member
Posts: 439
Joined: 2005-04-04
Senior Member
Posts: 439
Joined: 2005-04-04
#5681239 Posted on: 06/16/2019 11:25 AM
Can they make 8 Dimms memory board? or maybe 4ch 8 Dimms board?
Since now they are at X299 league with 3900X/3950X and it's need more memory dimms slots or quad Chanel memory.
*TR X599 will be another league, no cannibalization.
Can they make 8 Dimms memory board? or maybe 4ch 8 Dimms board?
Since now they are at X299 league with 3900X/3950X and it's need more memory dimms slots or quad Chanel memory.
*TR X599 will be another league, no cannibalization.
Evildead666
Senior Member
Posts: 1237
Joined: 2003-09-14
Senior Member
Posts: 1237
Joined: 2003-09-14
#5681243 Posted on: 06/16/2019 11:44 AM
Can they make 8 Dimms memory board? or maybe 4ch 8 Dimms board?
Since now they are at X299 league with 3900X/3950X and it's need more memory dimms slots or quad Chanel memory.
*TR X599 will be another league, no cannibalization.
The problem is the number of pins for the socket.
TR is so big, mainly due to the extra memory channels.
AM4 and AM5 will be dual channel.
Each memory leap DDR3/4/5 is about twice as fast as the last now, with a bit of regression, but doable
much cheaper than finding an extra 288 pins, per channel, for DDR4
edit : Also, i don't think its possible to do more than 2 Dimms per channel. So we are stuck at 4 Dimms, which is still quite good. 128GB max i think, with 32GB dimms.
Can they make 8 Dimms memory board? or maybe 4ch 8 Dimms board?
Since now they are at X299 league with 3900X/3950X and it's need more memory dimms slots or quad Chanel memory.
*TR X599 will be another league, no cannibalization.
The problem is the number of pins for the socket.
TR is so big, mainly due to the extra memory channels.
AM4 and AM5 will be dual channel.
Each memory leap DDR3/4/5 is about twice as fast as the last now, with a bit of regression, but doable
much cheaper than finding an extra 288 pins, per channel, for DDR4
edit : Also, i don't think its possible to do more than 2 Dimms per channel. So we are stuck at 4 Dimms, which is still quite good. 128GB max i think, with 32GB dimms.
er557
Senior Member
Posts: 397
Joined: 2002-07-24
Senior Member
Posts: 397
Joined: 2002-07-24
#5681251 Posted on: 06/16/2019 12:26 PM
I see I'm still future proof here with my dual haswell system, got 80 pcie 3.0 lanes, both gpus get x16, many expansion cards, 10x sata 6gbps + 4x sata marvell card, and an quad nvme m.2 card with full bandwidth, and have yet free lanes to spare. such are the spoils of workstation boards. Next on my list is not upgrades, but rather get an identical motherboard to keep for any case... As the cpus are unlikely to die anytime soon.
I see I'm still future proof here with my dual haswell system, got 80 pcie 3.0 lanes, both gpus get x16, many expansion cards, 10x sata 6gbps + 4x sata marvell card, and an quad nvme m.2 card with full bandwidth, and have yet free lanes to spare. such are the spoils of workstation boards. Next on my list is not upgrades, but rather get an identical motherboard to keep for any case... As the cpus are unlikely to die anytime soon.
asturur
Senior Member
Posts: 406
Joined: 2010-05-12
Senior Member
Posts: 406
Joined: 2010-05-12
#5681252 Posted on: 06/16/2019 12:51 PM
Yes for a workstation you are probably enough future proof.
For gaming you are probably in the 60fps range for as long as you want.
I recently upgrade from a i7 990x ( first gen ) to a ryzen 2700x and i was like 30% faster after 10 years.
Yes for a workstation you are probably enough future proof.
For gaming you are probably in the 60fps range for as long as you want.
I recently upgrade from a i7 990x ( first gen ) to a ryzen 2700x and i was like 30% faster after 10 years.
DmitryKo
Senior Member
Posts: 248
Joined: 2011-08-08
Senior Member
Posts: 248
Joined: 2011-08-08
#5681253 Posted on: 06/16/2019 12:58 PM
On the X570 half of the PCIe lanes are freely reconfigurable as SATA or PCIe on each individual lane, similarily to the CPU on-die x4 link (tough the latter is somewhat less capable with only 2 SATA lanes).
I'd expect X590 would retain such capability for some of its additional x4 PCIe PHY blocks.
it would basically have one M2 slot less than X570, but have a x8 link to the chipset
The X590 chipset is supposed to have additional PCIe lanes, so the primary M.2 slot would be routed through these lanes.On the X570 half of the PCIe lanes are freely reconfigurable as SATA or PCIe on each individual lane, similarily to the CPU on-die x4 link (tough the latter is somewhat less capable with only 2 SATA lanes).
I'd expect X590 would retain such capability for some of its additional x4 PCIe PHY blocks.
Evildead666
Senior Member
Posts: 1237
Joined: 2003-09-14
Senior Member
Posts: 1237
Joined: 2003-09-14
#5681257 Posted on: 06/16/2019 01:15 PM
The X590 chipset is supposed to have additional PCIe lanes, so the primary M.2 slot would be routed through these lanes.
On the X570 half of the PCIe lanes are freely reconfigurable as SATA or PCIe on each individual lane, similarily to the CPU on-die x4 link (tough the latter is somewhat less capable with only 2 SATA lanes).
I'd expect X590 would retain such capability for some of its additional x4 PCIe PHY blocks.
I was referring to the possibility of a x8 link to the chipset.
In that case, the cpu would have a x16 to the gpu, and the x8 to the chipset, and lose the m2 slot from the cpu (taken by the chipset).
From that, the extra x4 on the chipset, would be used for the x8 link to the cpu, so it would immediately negate any increase on the chipset side.
So, overall, you would have a x8 link between the cpu and chipset, but lose a M2 slot (compared to X570).
However, if you add a PLX PCIe 4.0 switch on the chipset x16 lanes in the mix, it becomes interesting.
The X590 chipset is supposed to have additional PCIe lanes, so the primary M.2 slot would be routed through these lanes.
On the X570 half of the PCIe lanes are freely reconfigurable as SATA or PCIe on each individual lane, similarily to the CPU on-die x4 link (tough the latter is somewhat less capable with only 2 SATA lanes).
I'd expect X590 would retain such capability for some of its additional x4 PCIe PHY blocks.
I was referring to the possibility of a x8 link to the chipset.
In that case, the cpu would have a x16 to the gpu, and the x8 to the chipset, and lose the m2 slot from the cpu (taken by the chipset).
From that, the extra x4 on the chipset, would be used for the x8 link to the cpu, so it would immediately negate any increase on the chipset side.
So, overall, you would have a x8 link between the cpu and chipset, but lose a M2 slot (compared to X570).
However, if you add a PLX PCIe 4.0 switch on the chipset x16 lanes in the mix, it becomes interesting.
DmitryKo
Senior Member
Posts: 248
Joined: 2011-08-08
Senior Member
Posts: 248
Joined: 2011-08-08
#5681265 Posted on: 06/16/2019 02:12 PM
X570 marketing materials count up to 24 lanes on the CPU side (x16 graphics, x4 storage and x4 downlink) and up to 16 lanes in the PCH (reconfigurable at x16, x8, x4, x1 granularity).
The news above imply 8 additional PCIe lanes in the X590 PCH for a total of 24, so that would be in comparison to the 16 peripheral lanes on the X570, excluding the chipset uplink lanes which are counted on the CPU side.
the extra x4 on the chipset, would be used for the x8 link to the cpu, so it would immediately negate any increase on the chipset side.
X570 marketing materials count up to 24 lanes on the CPU side (x16 graphics, x4 storage and x4 downlink) and up to 16 lanes in the PCH (reconfigurable at x16, x8, x4, x1 granularity).
The news above imply 8 additional PCIe lanes in the X590 PCH for a total of 24, so that would be in comparison to the 16 peripheral lanes on the X570, excluding the chipset uplink lanes which are counted on the CPU side.
Evildead666
Senior Member
Posts: 1237
Joined: 2003-09-14
Senior Member
Posts: 1237
Joined: 2003-09-14
#5681266 Posted on: 06/16/2019 02:14 PM
The news only implies an extra x4 lanes. 24 in total, and x4 for the uplink, so 20 left. 4 more than the X570 which has 16
edit : also, the chipset lanes are to be counted on both sides, chipset and cpu. Its the link between them. So they each lose x4 for their link.
X570 marketing materials count peripheral PCIe lanes separately from the CPU uplink. Since the news imply 8 additional PCIe lanes, for a total of 24 - that would be in comparison to the existing 16 peripheral lanes on the X570, excluding the chipset uplink lanes which are counted on the CPU side.
The news only implies an extra x4 lanes. 24 in total, and x4 for the uplink, so 20 left. 4 more than the X570 which has 16
edit : also, the chipset lanes are to be counted on both sides, chipset and cpu. Its the link between them. So they each lose x4 for their link.
illrigger
Senior Member
Posts: 145
Joined: 2017-02-16
Senior Member
Posts: 145
Joined: 2017-02-16
#5681283 Posted on: 06/16/2019 03:55 PM
The news only implies an extra x4 lanes. 24 in total, and x4 for the uplink, so 20 left. 4 more than the X570 which has 16
edit : also, the chipset lanes are to be counted on both sides, chipset and cpu. Its the link between them. So they each lose x4 for their link.
This. If you move the x4 from the m.2 slot on the CPU to the bus link, you have to lose another x4 on the chipset side, too. Of course, x590 would be a beefier chipset to account for this, but x570's already got a constant draw of 11W, and loaded draw of 15W. Nobody wants to put a CPU-sized HSF on their chipsets, so going denser on that side of things might require a die shrink (and the corresponding cost increase, since their 7nm capacity is all being used for CPU chiplet wafers at the moment). And, of course, moving to an x8 bus would just move the M.2 slot to there, and you'd end up saturating it if you put two SSDs in anyway. In the end there would be very little benefit overall for a lot of extra cost.
I think more likely they had planned x490 as a version with USB4, but it was not ready so they didn't launch it. Note the 40gbit of bandwidth set aside for USB 3.2 off the CPU, which is conveniently the same amount a USB4 link would need. They could then also give mobo makers the option of using the "pick one" options to be additional USB4 ports.
The news only implies an extra x4 lanes. 24 in total, and x4 for the uplink, so 20 left. 4 more than the X570 which has 16
edit : also, the chipset lanes are to be counted on both sides, chipset and cpu. Its the link between them. So they each lose x4 for their link.
This. If you move the x4 from the m.2 slot on the CPU to the bus link, you have to lose another x4 on the chipset side, too. Of course, x590 would be a beefier chipset to account for this, but x570's already got a constant draw of 11W, and loaded draw of 15W. Nobody wants to put a CPU-sized HSF on their chipsets, so going denser on that side of things might require a die shrink (and the corresponding cost increase, since their 7nm capacity is all being used for CPU chiplet wafers at the moment). And, of course, moving to an x8 bus would just move the M.2 slot to there, and you'd end up saturating it if you put two SSDs in anyway. In the end there would be very little benefit overall for a lot of extra cost.
I think more likely they had planned x490 as a version with USB4, but it was not ready so they didn't launch it. Note the 40gbit of bandwidth set aside for USB 3.2 off the CPU, which is conveniently the same amount a USB4 link would need. They could then also give mobo makers the option of using the "pick one" options to be additional USB4 ports.
Alessio1989
Senior Member
Posts: 1404
Joined: 2015-06-11
Senior Member
Posts: 1404
Joined: 2015-06-11
#5681301 Posted on: 06/16/2019 04:55 PM
I have a dream, I have a dream, one x590 MB with just one 10Gb ethernet port an everything filled with S-ATA III ports... A dream about a NAS/p2p server O___O
There would be little benefit from the extra 8 PCIe lanes in the PCH, as all these 24 lanes would map to the same 4-lane CPU uplink.
Now if they could reconfigure the CPU NVMe x4 link to double as the downlink lanes to the chipset...
This would a really nice solution...
I have a dream, I have a dream, one x590 MB with just one 10Gb ethernet port an everything filled with S-ATA III ports... A dream about a NAS/p2p server O___O
There would be little benefit from the extra 8 PCIe lanes in the PCH, as all these 24 lanes would map to the same 4-lane CPU uplink.
Now if they could reconfigure the CPU NVMe x4 link to double as the downlink lanes to the chipset...
This would a really nice solution...
Reddoguk
Senior Member
Posts: 1741
Joined: 2010-05-26
Senior Member
Posts: 1741
Joined: 2010-05-26
#5681304 Posted on: 06/16/2019 05:06 PM
maybe the 590X supports DDR5 memory which isn't that far off according to some websites > Release date 2019 (estimate)
maybe the 590X supports DDR5 memory which isn't that far off according to some websites > Release date 2019 (estimate)
Alessio1989
Senior Member
Posts: 1404
Joined: 2015-06-11
Senior Member
Posts: 1404
Joined: 2015-06-11
#5681307 Posted on: 06/16/2019 05:11 PM
The memory controller is integrated in the CPU package..
The FCH/PCH has nothing to do with the supported SDRAM type, you can also disable it in some MBs...
maybe the 590X supports DDR5 memory which isn't that far off according to some websites > Release date 2019 (estimate)
The memory controller is integrated in the CPU package..
The FCH/PCH has nothing to do with the supported SDRAM type, you can also disable it in some MBs...
Click here to post a comment for this news story on the message forum.
Senior Member
Posts: 1237
Joined: 2003-09-14
Maybe its a TDP choice ?
They could do a WS board, but just 4 extra PCIe lanes is weak, and X570 are going to be expensive anyway.
An x8 link to the chipset ? (get rid of any bottlenecks, perceived or otherwise).