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AMD Working on Vertical (3D) Stacking of DRAM onto processors
News from the other side of the globe reaches us and is saying that AMD is working hard to embed DRAM and System Memory onto processors into one single package. The RAM would get connected through silicon-through-channels.
In many segments manufacturers are already working on similar technologies, look at HBM2 and NAND 3D Vertical stacking. For a processor, this, however, is new as the aforementioned technologies are based on a package-on package design. .The new tech would not make the actual memory faster but will make it work more efficient in overall performance.
Intel is doing similar things with under the codename foveros
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MBTP
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Senior Member
Posts: 142
Joined: 2015-05-25
#5651197 Posted on: 03/18/2019 04:04 PM
Sincerely, i don't see why anyone would be concerned by upgradability, i think this is the right, and probably the only way foward.
1. This can co-exists with DDR ram stick modules.
2. Smartphones are like this already, seems most people don't care.
3. The major market for this being small portable notebooks, ultrabooks, and laptops, are generally not upgradable anyway, and when they are most people don't upgrade ever.
4. The overall cost of the chiplets will be in no time very cheap.
5. This style will probably be sold in packages so in the end will be cheaper to the end consumer, with highly optimized cooling systems.
6. This could work as a L4 cache or not as someone said already, and let's remeber that Non volatile "rams" are coming to the consumer market, this could be extremely compact with it.
7. This could be the next step to modular systems, as antagonic this statement can sound, with AM4 as and example, more optimized cooling systems, less components on the motherboard itself, reduced motherboard footprint, problems like having to upgrade a motherboard just to support the next memory technology will not need to exist.
Ex: APU+HBM2.0 "AM5" socket, will probably be able to be upgraded to APU+HBM3.0/4.0, since the limitation will not be on the MB traces, but you be limited maybe on the I/O speed of last gen. This will be highly dependent on MB suppliers and CPU sockets...
Sincerely, i don't see why anyone would be concerned by upgradability, i think this is the right, and probably the only way foward.
1. This can co-exists with DDR ram stick modules.
2. Smartphones are like this already, seems most people don't care.
3. The major market for this being small portable notebooks, ultrabooks, and laptops, are generally not upgradable anyway, and when they are most people don't upgrade ever.
4. The overall cost of the chiplets will be in no time very cheap.
5. This style will probably be sold in packages so in the end will be cheaper to the end consumer, with highly optimized cooling systems.
6. This could work as a L4 cache or not as someone said already, and let's remeber that Non volatile "rams" are coming to the consumer market, this could be extremely compact with it.
7. This could be the next step to modular systems, as antagonic this statement can sound, with AM4 as and example, more optimized cooling systems, less components on the motherboard itself, reduced motherboard footprint, problems like having to upgrade a motherboard just to support the next memory technology will not need to exist.
Ex: APU+HBM2.0 "AM5" socket, will probably be able to be upgraded to APU+HBM3.0/4.0, since the limitation will not be on the MB traces, but you be limited maybe on the I/O speed of last gen. This will be highly dependent on MB suppliers and CPU sockets...
Venix
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Senior Member
Posts: 2524
Joined: 2016-08-01
#5651243 Posted on: 03/18/2019 06:19 PM
With apus this is not a surprise apus are very much bottlenecked by ddr4 and ddr5 will not be enough. Tiered storage is how computers work since forever l1-l2-l3-ddr now it will be l1-l2-l3-stuck-ddr
With apus this is not a surprise apus are very much bottlenecked by ddr4 and ddr5 will not be enough. Tiered storage is how computers work since forever l1-l2-l3-ddr now it will be l1-l2-l3-stuck-ddr
Richard Nutman
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Posts: 254
Joined: 2018-08-30
#5651247 Posted on: 03/18/2019 06:33 PM
Broadwell DT already did this with 128MB of EDRAM for the integrated gpu. When using discrete graphics it acted like a L4 cache. It gave some serious performance boosts in games.
It's a shame this tech didn't take off more.
Broadwell DT already did this with 128MB of EDRAM for the integrated gpu. When using discrete graphics it acted like a L4 cache. It gave some serious performance boosts in games.
It's a shame this tech didn't take off more.
fantaskarsef
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Posts: 13360
Joined: 2014-07-21
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Posts: 13360
Joined: 2014-07-21
#5651249 Posted on: 03/18/2019 06:39 PM
There is a place and market for such an implementation. Most OEM products could be done like that, notebooks as well as embedded versions ofc. Generally products which are hardly upgraded in performance hardware (rather with more storage if at all). That summed up makes what, 90% of the PC market?
There is a place and market for such an implementation. Most OEM products could be done like that, notebooks as well as embedded versions ofc. Generally products which are hardly upgraded in performance hardware (rather with more storage if at all). That summed up makes what, 90% of the PC market?
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Finally
I know of this for some time.
But we need 3D+2.5D Stacked GPUs chiplets w Infinity Fabric + HBM