AMD shares details on 8-core Seattle ARM architecture

AMD released some details about their upcoming eight-core ARM Cortex-A57 based server processor developped under codename Seattle. Seattle's eight 64-bit Cortex-A57 cores are arranged in four dual-core modules, each of which shares 1MB of L2 cache. That makes for 4MB of L2 cache in all.

The four dual-core modules also have access to an 8MB pool of shared L3 cache, which links up all the cores, coprocessors, memory controller, and I/O. The L2 and L3 caches are 16-way associative with ECC protection, and Seattle's cache network (which also includes L1 instruction and data caches) is fully coherent, meaning there should be no discrepancies between instances of the same data stored at different levels of the cache as techreport notes:

Seattle has dual memory channels that support either DDR3 or DDR4 RAM with ECC protection. Each of these 72-bit channels can accommodate a maximum of two modules (of the RDIMM, SO-DIMM, and UDIMM variety, depending on what hardware makers choose) with a peak transfer rate of 1866 MT/s. In all, each Seattle CPU can address up to 128GB of RAM spread across four 32GB modules.

On the I/O front, Seattle can drive eight Serial ATA 6Gbps ports, two 10Gbps Ethernet ports, and eight lanes of PCI Express Gen3 connectivity. The PCIe connectivity can be laid out in three configurations: with a single x8 controller, with two controllers in an x4/x4 arrangement, and with three controllers in an x4/x2/x2 arrangement. Each controller can operate at Gen1, Gen2, or Gen3 speeds without affecting the speed of the other controllers. The same goes for the SATA ports, which can also support legacy drives capped at 3Gbps or 1.5Gbps speeds.