AMD Radeon 390X WCE - Water-Cooled Edition
Yep and then there is the slide after the break, that surfaced on the web over the weekend, it confirms leaks about R9 390X 8GB HBM. Anyway check after the break to see what is mentioned in the slide, that's IF it isn't a fake of course.
The leaker (videocardz) claims this slide is a part of in-house presentation called ‘2015 Future of Radeon’ that will be shown next week to AIB partners (not to public).
AMD Radeon R9 390X WCE:
Next iteration of the highly successful GCN design
- Up to 4096 shader units
- Full DirectX 12_Tier 3 implementation
- Optimized for 4K gaming & beyond
- First ever GPU designed for VR immersion
- Special enthusiast water-cooled edition
- Up to 8GB of ultra-high bandwidth HBM video memory
- Hardware H.265 decoding and over 4x the previous H.264 encoding speed, enabling smooth live streaming
- Enhanced ZeroCore functionallity
Granted the screenshot does look like an AMD slide, the text however has typo's (functionality is misspelled) and weird wording like "DirectX 12_Tier 3 implementation" which is uncommon for AMD as everything is vetted and goes through a screening process.
Ah well .. here's that slide:
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Senior Member
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Up to 8GB, might mean theres 2x versions, a 4GB and an 8GB.
Senior Member
Posts: 2976
Joined: 2007-04-12
i am kinda confused by this hbm memory..
if the 4gb version has a 4 stacks of hbm running at 1024 bit per stack yielding a 4096bit memory bus which gives 640G/b memory bandwidth so the 8gig version will yield 1,8 T/b of memory bandwidth?
Senior Member
Posts: 7214
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loads of bandwidth that won't be a huge problem in future...
Senior Member
Posts: 13807
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This thing coming out anytime this year? I mean seriously.. AMD finally gets a leg up with HBM and then squanders it by taking forever to actually release. Nvidia's going to have HBM with pascal by this time next year -- AMD needs to get the 390x out now.
Posts: 22220
Joined: 2008-07-14
4096bit only. 8GB is doable by 2 simple ways:
- double density of each stack
- 8 stacks instead of 4
Those 1GB per HBM brick were ready last xmas, AMD's waits most likely for double density per stack.
The prior explanation of HBM memory bus was that for every 1GB of HBM, there would be a 1024bit memory path. I simply went based on the explanation. I didn't say my statement was entirely accurate. I said it would be accurate if the previous explanation was accurate. In the case of double density memory stacks, the previous explanation of the HBM memory bus would be wrong.
Based on the previous explanation, 8 stacks would double the memory bus width from 4096bit to 8192bit.