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AMD Linux driver reveals preliminary PCI-Express 4.0 support
While the need for PCI-Express 4.0 seems a bit redundant and far-fetched for any near future graphics card it now looks like it that the 7nm Vega20 that was announced on Computex, might be PCIe 4.0 compatible. Which has been an ongoing rumor ever since the beginning.
Earlier last year in October we already talked about Generation 4, the spec now is final. PCI-Express Gen 4.0 will offer 16 GT/s per PCI-Express lane which is double that of the 8 GT/s on the current PCI-Express Gen 3.0 specification. If you multiply 16 GT/s per lane bandwidth that translates into 1.97 GB/s for x1 devices, 7.87 GB/s for x4, 15.75 GB/s for x8, and 31.5 GB/s for x16 devices. The guys from Computerbase spotted an entry in the Linux AMD driver.
Contrary to say your SATA ports, PCI Express has moved well beyond the needs of any graphics cards. Currently, nearly every IO device routes data through PCIe to send signals back to the CPU and across the platform. It is expected to see rapid adoption of the new standard for storage and networking products (10 GBit/s links). NVMe SSDs using PCIe 3.0 x4, for example, reached the usable limit of the interface, ergo future NAND storage devices could benefit far better from this new standard. Meanwhile PCI-Express also already is in development at PCI-Sig, I added the numbers but that will take many years to see implemented.
| PCIe Version | Line Code | Transfer Rate | x1 Bandwidth | x4 | x8 | x16 |
|---|---|---|---|---|---|---|
| 1.0 | 8b/10b | 2.5 GT/s | 250 MB/s | 1 GB/s | 2 GB/s | 4 GB/s |
| 2.0 | 8b/10b | 5 GT/s | 500 MB/s | 2 GB/s | 4 GB/s | 8 GB/s |
| 3.0 | 128b/130b | 8 GT/s | 984.6 MB/s | 3.938 GB/s | 7.877 GB/s | 15.754 GB/s |
| 4.0 | 128b/130b | 16 GT/s | 1.969 GB/s | 7.877 GB/s | 15.754 GB/s | 31.508 GB/s |
| 5.0 | 128b/130b | 32 GT/s | 3.938 GB/s | 15.754 GB/s | 31.508 GB/s | 63.016 GB/s |
schmidtbag
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#5561355 Posted on: 06/29/2018 02:49 PM
For current-gen AMD GPUs, probably not. But, I imagine Volta GPUs demand more bandwidth than 3.0 @ x8 can offer.
EDIT:
As far as I'm concerned, the real benefit of higher-bandwidth PCIe lanes comes down to everything that uses fewer than x4 lanes (like M.2, x1 slots, Thunderbolt, etc). We need more bandwidth there; at this point, we could probably ditch x16 slots because I'm not sure we're really ever going to see hardware (of the same generation) take advantage of those ever again.
Are we even close to saturating PCIe 3.0 yet?
For current-gen AMD GPUs, probably not. But, I imagine Volta GPUs demand more bandwidth than 3.0 @ x8 can offer.
EDIT:
As far as I'm concerned, the real benefit of higher-bandwidth PCIe lanes comes down to everything that uses fewer than x4 lanes (like M.2, x1 slots, Thunderbolt, etc). We need more bandwidth there; at this point, we could probably ditch x16 slots because I'm not sure we're really ever going to see hardware (of the same generation) take advantage of those ever again.
Silva
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Posts: 1433
Joined: 2013-06-04
#5561366 Posted on: 06/29/2018 03:19 PM
It's not only about saturating but efficiency too. Current SSD can already max PCIe3.0 4x for example.
Business needs this badly to improve performance. As for us consumers, CPUs have a limited number of lanes because they're expensive to make. So, if we need less lanes to power the same things, we get cheaper products or more feature rich products for the same price!
Currently some boards with 2 nvme slots have one running at 3.0 and the other at 2.0 through the chipset. An SSD connected through the chipset will have its performance degraded by half.
Are we even close to saturating PCIe 3.0 yet?
It's not only about saturating but efficiency too. Current SSD can already max PCIe3.0 4x for example.
Business needs this badly to improve performance. As for us consumers, CPUs have a limited number of lanes because they're expensive to make. So, if we need less lanes to power the same things, we get cheaper products or more feature rich products for the same price!
Currently some boards with 2 nvme slots have one running at 3.0 and the other at 2.0 through the chipset. An SSD connected through the chipset will have its performance degraded by half.
nosirrahx
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Joined: 2013-04-05
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Posts: 328
Joined: 2013-04-05
#5561367 Posted on: 06/29/2018 03:21 PM
For current-gen AMD GPUs, probably not. But, I imagine Volta GPUs demand more bandwidth than 3.0 @ x8 can offer.
EDIT:
As far as I'm concerned, the real benefit of higher-bandwidth PCIe lanes comes down to everything that uses fewer than x4 lanes (like M.2, x1 slots, Thunderbolt, etc). We need more bandwidth there; at this point, we could probably ditch x16 slots because I'm not sure we're really ever going to see hardware (of the same generation) take advantage of those ever again.
Gen 4 X 4 lanes could handle just about anything we need. It could allow for standard 4 X risers in cases to more conveniently mount GFX cards.
For current-gen AMD GPUs, probably not. But, I imagine Volta GPUs demand more bandwidth than 3.0 @ x8 can offer.
EDIT:
As far as I'm concerned, the real benefit of higher-bandwidth PCIe lanes comes down to everything that uses fewer than x4 lanes (like M.2, x1 slots, Thunderbolt, etc). We need more bandwidth there; at this point, we could probably ditch x16 slots because I'm not sure we're really ever going to see hardware (of the same generation) take advantage of those ever again.
Gen 4 X 4 lanes could handle just about anything we need. It could allow for standard 4 X risers in cases to more conveniently mount GFX cards.
Evildead666
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Joined: 2003-09-14
Senior Member
Posts: 1304
Joined: 2003-09-14
#5561369 Posted on: 06/29/2018 03:26 PM
Seeing as both the DMI interface on Intel, and the AMD equivalent, both use effectively PCIe 3.0 x4 interfaces, yes is the answer.
Having a PCIe 4.0 x4 interface between the CPU and the chipset will be a godsend to motherboard makers everywhere.
Are we even close to saturating PCIe 3.0 yet?
Seeing as both the DMI interface on Intel, and the AMD equivalent, both use effectively PCIe 3.0 x4 interfaces, yes is the answer.
Having a PCIe 4.0 x4 interface between the CPU and the chipset will be a godsend to motherboard makers everywhere.
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Are we even close to saturating PCIe 3.0 yet?