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Guru3D.com » News » AMD EPYC Milan-X specifications leak, revealing up to 64 cores, 280W TDP, 768MB L3 cache.

AMD EPYC Milan-X specifications leak, revealing up to 64 cores, 280W TDP, 768MB L3 cache.

by Hilbert Hagedoorn on: 09/16/2021 03:03 PM | source: videocardz via @ExecuFix, @momomo_us | 15 comment(s)
AMD EPYC Milan-X specifications leak, revealing up to 64 cores, 280W TDP, 768MB L3 cache.

The AMD EPYC Milan-X server CPU platform has a layered L3 cache, which significantly increases the amount of available cache, bringing it towards max 768MB.

AMD Milan-X, which was first spotted by ExecutableFix in May, is a server CPU family that takes advantage of AMD's latest X3D packaging technology, according to the company (3D V-Cache). According to the most recent leak, it would combine AMD Genesis-IO die and stacked chiplets with a vast third-level cache, maybe up to 768MB.

Executable Fix (via videocardz) provides up-to-date information about the series, including the full specifications of the AMD EPYC 7003 CPUs, as well as links to other useful resources. According to the leaker, the flagship Milan-X processor, codenamed 7773X, will have 64 cores and 128 threads with a total power consumption of 280W. This CPU, along with the other 'downgraded' components, would have 768MB L3 cache, which is over three times the amount of L3 cache found in the original Milan series (up to 256MB). The specifications for the 7573X, 7473X, and 7373X were also revealed. The core counts for these SKUs would be 32, 24, and 16 cores, respectively. TDP would be 240W, however, the L3 cache would be 768MB on both the 7473X and 7373X.

In this case, the 768MB L3 cache shows that each Core Complex has 32MB, similar to the original Milan configuration, but the 64MB V-Cache is linked to each CCD. That is, each processor has 8x32 MB of main memory plus 8x64 MB of virtual memory. In contrast to AMD's Ryzen processors, which include 3D VRAM, the Milan-X series has not been officially confirmed.



AMD EPYC Milan-X specifications leak, revealing up to 64 cores, 280W TDP, 768MB L3 cache.




« VIA Labs Announces Launch of USB4 Device Silicon · AMD EPYC Milan-X specifications leak, revealing up to 64 cores, 280W TDP, 768MB L3 cache. · Arctic Announces LGA1700 Mounting Kits for Intel Core Alder Lake Procs (available for 6 Euro) »

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schmidtbag
Senior Member



Posts: 6476
Joined: 2012-11-10

#5947345 Posted on: 09/17/2021 05:40 AM
I'd be really curious to see what would happen if someone were to put in a 64MB (not a typo) stick of RAM in, install Windows XP, and play some early 2000s game just to see how it runs. Obviously it's utterly useless, but it's weird to think about having more cache than you have RAM, and enough cache to actually run your entire system and a simple game. Hard to wrap your head around.

BLEH!
Senior Member



Posts: 6219
Joined: 2010-10-17

#5947431 Posted on: 09/17/2021 12:41 PM
I'd be really curious to see what would happen if someone were to put in a 64MB (not a typo) stick of RAM in, install Windows XP, and play some early 2000s game just to see how it runs. Obviously it's utterly useless, but it's weird to think about having more cache than you have RAM, and enough cache to actually run your entire system and a simple game. Hard to wrap your head around.

CacheRAMdrive? Cachedrive?

Alessio1989
Senior Member



Posts: 2264
Joined: 2015-06-11

#5947452 Posted on: 09/17/2021 02:32 PM
768 L3 cache



Denial
Senior Member



Posts: 13711
Joined: 2004-05-16

#5947458 Posted on: 09/17/2021 02:55 PM
The latency is still, surely, an order of magnitude lower than accessing DDR?


Yeah - the idea behind IBM's implementation is that it massively reduces L3 latency at the expense of slightly increased L2. If you get lucky, you can hit L3 for nearly identical latency as L2 but in the vast majority of scenarios the latency of your L3 is going to be significantly faster than traditional L3 - for example the L3 seen here. In traditional PC workloads you're not going to see much of a benefit but in use cases IBM's cloud servers, or Epyc's servers are being used, having a fast L3 is extremely useful.

Keep in mind IBM's system is also scaling up to ~512mb of combined L2/L3 per module and 8GB of cache (virtual L4 in this case) in a 32 chip system.

AMD's stacking here would be adjacent to this.

kapu
Senior Member



Posts: 5288
Joined: 2006-12-22

#5947462 Posted on: 09/17/2021 03:02 PM
In before 1-2 gigs of cache and cache drives - can it run crysis from cache ?

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