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AMD EPYC Milan-X specifications leak, revealing up to 64 cores, 280W TDP, 768MB L3 cache.
The AMD EPYC Milan-X server CPU platform has a layered L3 cache, which significantly increases the amount of available cache, bringing it towards max 768MB.
AMD Milan-X, which was first spotted by ExecutableFix in May, is a server CPU family that takes advantage of AMD's latest X3D packaging technology, according to the company (3D V-Cache). According to the most recent leak, it would combine AMD Genesis-IO die and stacked chiplets with a vast third-level cache, maybe up to 768MB.
Executable Fix (via videocardz) provides up-to-date information about the series, including the full specifications of the AMD EPYC 7003 CPUs, as well as links to other useful resources. According to the leaker, the flagship Milan-X processor, codenamed 7773X, will have 64 cores and 128 threads with a total power consumption of 280W. This CPU, along with the other 'downgraded' components, would have 768MB L3 cache, which is over three times the amount of L3 cache found in the original Milan series (up to 256MB). The specifications for the 7573X, 7473X, and 7373X were also revealed. The core counts for these SKUs would be 32, 24, and 16 cores, respectively. TDP would be 240W, however, the L3 cache would be 768MB on both the 7473X and 7373X.
In this case, the 768MB L3 cache shows that each Core Complex has 32MB, similar to the original Milan configuration, but the 64MB V-Cache is linked to each CCD. That is, each processor has 8x32 MB of main memory plus 8x64 MB of virtual memory. In contrast to AMD's Ryzen processors, which include 3D VRAM, the Milan-X series has not been officially confirmed.
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Denial
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#5947225 Posted on: 09/16/2021 07:00 PM
yes for traditional enterprise you are probably right as long as "better" means cheaper.
but for high tech enterprise nothing beats on die cache. and massive on die cache at that.
It is on die - 256MB of Shared L2/L3 virtual cache per 8 core chip. It obviously comes with a latency penalty but the benefits of the L3 being shared with the L2 supposedly outweighs that.
yes for traditional enterprise you are probably right as long as "better" means cheaper.
but for high tech enterprise nothing beats on die cache. and massive on die cache at that.
It is on die - 256MB of Shared L2/L3 virtual cache per 8 core chip. It obviously comes with a latency penalty but the benefits of the L3 being shared with the L2 supposedly outweighs that.
Kaarme
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#5947248 Posted on: 09/16/2021 08:28 PM
The latency is still, surely, an order of magnitude lower than accessing DDR?
It is on die - 256MB of Shared L2/L3 virtual cache per 8 core chip. It obviously comes with a latency penalty but the benefits of the L3 being shared with the L2 supposedly outweighs that.
The latency is still, surely, an order of magnitude lower than accessing DDR?
user1
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Posts: 1974
Joined: 2016-01-29
#5947293 Posted on: 09/16/2021 10:53 PM
This is better, this is legit l3 cache, thats added on top of the existing cache and connected via tsvs (Through Silicon Via), there is no latency penalty, unlike an l4 cache which would be slower.
That's a LOOOOOOT of cache! Is this like the L4 that intel stuck onto the desktop Broadwell parts then, or something else? I remember that giving a rather spicy boost to performance that kept the architecture on par with far more recent things...
This is better, this is legit l3 cache, thats added on top of the existing cache and connected via tsvs (Through Silicon Via), there is no latency penalty, unlike an l4 cache which would be slower.
tunejunky
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#5947297 Posted on: 09/16/2021 11:53 PM
can you imagine (crazy sci - fi music) we're living in the fuuuutuuure
Hehe i guess we are not more than a year ot two to get cpus with 1gb cache ! Not on desktop thought :p
can you imagine (crazy sci - fi music) we're living in the fuuuutuuure
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Hehe i guess we are not more than a year ot two to get cpus with 1gb cache ! Not on desktop thought :p