Samsung: 1.4 nm Process Technology by 2027
Samsung Electronics, a world leader in advanced semiconductor technology, announced today a strengthened business strategy for its Foundry Business with the introduction of cutting-edge technologies at its annual Samsung Foundry Forum event.
With significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.
During the event, Samsung also outlined steps its Foundry Business is taking in order to meet customers' needs, including: foundry process technology innovation, process technology optimization for each specific applications, stable production capabilities, and customized services for customers. "The technology development goal down to 1.4 nm and foundry platforms specialized for each application, together with stable supply through consistent investment are all part of Samsung's strategies to secure customers' trust and support their success," said Dr. Si-young Choi, president and head of Foundry Business at Samsung Electronics. "Realizing every customer's innovations with our partners has been at the core of our foundry service."
Showcasing Samsung's Advanced Node Roadmap Down to 1.4 nm in 2027
With the company's success of bringing the latest 3 nm process technology to mass production, Samsung will be further enhancing gate-all-around (GAA) based technology and plans to introduce the 2 nm process in 2025 and 1.4 nm process in 2027.
While pioneering process technologies, Samsung is also accelerating the development of 2.5D/3D heterogeneous integration packaging technology to provide a total system solution in foundry services.
Through continuous innovation, its 3D packaging X-Cube with micro-bump interconnection will be ready for mass production in 2024, and bump-less X-Cube will be available in 2026.
Proportion of HPC, Automotive and 5G to be More than 50% by 2027
Samsung actively plans to target high-performance and low-power semiconductor markets such as HPC, automotive, 5G and the Internet of Things (IoT).
To better meet customers' needs, customized and tailored process nodes were introduced during this year's Foundry Forum. Samsung will enhance its GAA-based 3 nm process support for HPC and mobile, while further diversifying the 4 nm process specialized for HPC and automotive applications.
For automotive customers specifically, Samsung is currently providing embedded non-volatile memory (eNVM) solutions based on 28 nm technology. In order to support automotive-grade reliability, the company plans to further expand process nodes by launching 14 nm eNVM solutions in 2024 and adding 8 nm eNVM in the future. Samsung has been mass producing 8 nm RF following 14 nm RF, and 5 nm RF is currently in development.
"Shell-First" Operation Strategy to Respond to Customer Needs in a Timely Manner
Samsung plans to expand its production capacity for the advanced nodes by more than three times by 2027 compared to this year.
Including the new fab under construction in Taylor, Texas, Samsung's foundry manufacturing lines are currently in five locations: Giheung, Hwaseong, and Pyeongtaek in Korea; and Austin and Taylor in the United States.
At the event, Samsung detailed its "Shell-First" strategy for capacity investment, building cleanrooms first irrespective of market conditions. With cleanrooms readily available, fab equipment can be installed later and set up flexibly as needed in line with future demand. Through the new investment strategy, Samsung will be able to better respond to customers' demands.
Investment plans in a new "Shell-First" manufacturing line in Taylor, following the first line announced last year, as well as potential expansion of Samsung's global semiconductor production network were also introduced.
Expanding the SAFE ecosystem to strengthen customized services
Following the "Samsung Foundry Forum," Samsung will hold the "SAFE Forum'"(Samsung Advanced Foundry Ecosystem) on October 4th. New foundry technologies and strategies with ecosystem partners will be introduced encompassing areas such as Electronic Design Automation (EDA), IP, Outsourced Semiconductor Assembly and Test (OSAT), Design Solution Partner (DSP) and the Cloud.
In addition to 70 partner presentations, Samsung Design Platform team leaders will introduce the possibility of applying Samsung's processes such as Design Technology Co-Optimization for GAA and 2.5D/3DIC.
As of 2022, Samsung provides more than 4,000 IPs with 56 partners, and is also cooperating with nine and 22 partners in the design solution and EDA, respectively. It also offers cloud services with nine partners and packaging services with 10 partners.
Along with its ecosystem partners, Samsung provides integrated services that support solutions from IC design to 2.5D/3D packages.
Through its robust SAFE ecosystem, Samsung plans to identify new fabless customers by strengthening customized services with improved performance, rapid delivery and price competitiveness, while actively attracting new customers such as hyperscalers and start-ups.
Starting in the United States (San Jose) on October 3rd, the "Samsung Foundry Forum" will be sequentially held in Europe (Munich, Germany) on the 7th, Japan (Tokyo) on the 18th, and Korea (Seoul) on the 20th, through which customized solutions for each region will be introduced. A recording of the event will be available online from the 21st for those who were unable to attend in person.
Senior Member
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Joined: 2016-08-01
Again people fall for the trap of the marketing naming .... 1.4 is not really nm not as they where traditionally used . The tsmc 16/14 glofo 14 are the old 20nm but finfet 20nm traditional existed but the yields where so poor it was more expensive and it really did not offer much for the cost this is why we where stuck to 28nm for so long . The 16/14 nodes where renamed for marketing reason the tsmc 7nm are more in line with Intel's 10 nm density wise and the 5nm with Intel 7 .... Although not all waffers are the same between Intel Samsung Intel and tsmc and the density etc is not 1:1 identical. Honestly the most fair naming would be nand gates count per 1mm²
Senior Member
Posts: 14289
Joined: 2014-07-21
Here's what I don't get:
If they already know 1.4nm is possible, what exactly is preventing them from just skipping right to that? It's one thing where you're limited to how small you can get because you need an entirely new process, but it seems to me (and maybe I'm wrong) that for a lot of semiconductor producers, they're mostly just fine-tuning their process. I understand this is no simple task but I imagine the R&D is less expensive and time consuming to push the equipment to their physical limits rather than go in these incremental stages.
Yield rates most likely. Even if you can do 1.4nm, it doesn't say it's commercially feasible at this time.
Senior Member
Posts: 14040
Joined: 2004-05-16
Understood, but that's why I said it might make more sense to spend a little more time and money just skipping straight to the smallest size the technology can theoretically handle.
You're describing intels 10nm. In like 2015 they tried to moonshot down (lol) to a significantly smaller process but ended up in the weeds until ASML effectively bailed them out years later.
It's easy to demonstrate this stuff in a lab. It's much harder to pilot and in some cases it's impossible to mass produce.
If you don't go through the steps you might find your self several billion in a hole with little to show for it.