The Phenom II X6 1100T processor

The Phenom II X6 1100T Processor

Armed with a 3.3 GHz base clock frequency that can Turbo to 3.7 GHz, today a new six-core processor from AMD sees the light. It is actually AMD's fourth six-core processor that sits on top of the list right before the AMD Phenom II X6 1090T, 1075T and AMD Phenom II X6 1055T.

AMD really pushes the 45nm SOI node to manufacture the newer model Phenom II X6 processors. The processor itself is made at Fab 1 module 1 in Dresden and accounts for 904 million transistors squeezed into the 346 mm2 die.

Now there are faster clocked Phenom II processors for lighter-threaded workloads available like the PII X4 970 at 3.5 GHz, but for those who need the processing bandwidth and multi-tasking capability of a true 6-core processor, the Phenom II X6 is an affordable and quite powerful option.

So the flagship AMD processor product runs at 3.3 GHz (3.7 GHz Turbo) at a full bi-directional 2.0 GHz HT 3.0 speed... Its voltage range is remains 1.125 V -1.40 V.

Tagged at an MSRP of just 265 USD the Phenom II X6 1100T processor will drive the other six-core processors down in price. The 1090T for example already dropped to 235 USD.

• Model Number & Core Frequency: X6 1100T / 3.7 GHz (Turbo) / 3.3 GHz (Base)
• OPN: HDE00ZFBK6DGR
• L1 Cache Sizes: 64 K of L1 instruction and 64 K of L1 data cache per core (768 KB total L1 per processor)
• L2 Cache Sizes: 512 KB of L2 data cache per core (3 MB total L2 per processor)
• L3 Cache Size: 6 MB (shared)
• Total Cache (L2+L3): 9 MB
• Memory Controller Type: Integrated 128-bit wide memory controller
• Memory Controller Speed: Up to 2.0 GHz with Dual Dynamic Power Management
• Types of Memory Supported: Unregistered DIMMs up to PC2-8500 (DDR2-1066 MHz) -AND- PC3-10600 (DDR3 1333 MHz)
• HyperTransport 3.0 Specification: One 16-bit/16-bit link @ up to 4.0 GHz full duplex (2.0 GHz x2)
• Total Processor-to-System Bandwidth: Up to 37.3 GB/s total bandwidth [Up to 21.3 GB/s memory bandwidth (DDR3-1333) + 16.0 GB/s (HT3)]
• Up to 33.1GB/s total bandwidth [Up to 17.1 GB/s memory bandwidth (DDR2-1066) + 16.0GB/s (HT3)]
• Packaging: Socket AM3 938-pin organic micro pin grid array (micro-PGA)
• Fab location: GLOBALFOUNDARIES Fab 1 module 1 in Dresden, Germany (formerly AMD Fab 36)
• Process Technology: 45-nanometer DSL SOI (silicon-on-insulator) technology
• Approximate Die Size: 346mm2
• Approximate Transistor count: Similar to Istanbuls ~904 million
• Max TDP: 125 Watts
• AMD Codename: Thuban

The Thermal Design Power (TDP) is the average maximum power a processor can dissipate while running commercially available software. TDP is primarily used as a guideline for manufacturers of thermal solutions (heatsinks/fans, etc.) which tells them how much heat their solution should dissipate. TDP is not the maximum power the CPU may generate - there may be periods of time when the CPU dissipates more power than designed, in which case either the CPU temperature will rise closer to the maximum, or special CPU circuitry will activate and add idle cycles or reduce CPU frequency with the intent of reducing the amount of generated power.

The six-core processors all have a fair TDP (peak Wattage at 125W) but overall much better power management thanks to the fact that hardware C1E is implemented in the CPU, allowing the processor to throttle up and down real fast, core independent. That makes it an interesting change as it allows for faster switching of power states, making it more efficient whilst consuming less power and heat.

Let's go inside the processor then. This Phenom II X6 part is based on AMD's 45nm Silicon On Insulator process technology and has a total of 3 MB L2 cache; that's 512 KB per core. The Phenom II X6 can address 6 MB L3 cache shared among the cores as a buffer, so it can exchange data in-between the six logical cores. So that's 9 MB of cache and we have not even accounted for another 768 KB total L1 per processor. So all the variables are exactly the same as the latest generation Phenom II processors, just multiplied per core. Here's the bullet on that:

• 768 KB L1 Cache (Instruction + Data): 128 KB x6 (64 KB + 64 KB for each core)
• 3 MB L2 Cache: 512 KB x6 (hexacore)
• 6 MB L3 Cache: 6 MB Shared L3

L3 is where a lot of the magic happens and is probably the reason for Phenom II's success. Well, that and the flexible and high clock frequencies of course.

Turbo Core

The T in the model number indicates the product supports Turbo Core. AMD's Phenom II X6 series is equipped with a Turbo feature much like Intel's Core i5/7 series has. Turbo Core will be able to increase the operational frequencies of three active cores by up to 500MHz (depending on the processor) if an application can't use all six cores.

All monitoring and clock/voltage management is exclusively handled by the CPU, so this is not a quick software fix. Turbo Core is triggered based on operating conditions and application load demand. When power consumption is below the CPU's TDP, the technology puts the three used cores in a boost-enabled P-state.

This means that, should the application demand it, those cores will be able to increase their clocks by an amount dependent on the processing workload. This approach has more than one advantage. Since cores don't need to operate at the same frequency, each will only be pushed higher if the application demands it. As such, no extra power will be spent on unnecessary overclocking.

• The 125 W TDP AMD Phenom II X6 1100T @ 3.3 GHz with AMD Turbo Core @ 3.7 GHz
• The 125 W TDP AMD Phenom II X6 1090T @ 3.2 GHz with AMD Turbo Core @ 3.6 GHz
• The 125 W TDP AMD Phenom II X6 1075T @ 3.0 GHz with AMD Turbo Core @ 3.5 GHz
• The 125 W TDP AMD Phenom II X6 1055T @ 2.8 GHz with AMD Turbo Core @ 3.3 GHz.

When Turbo Core is activated the clocks of the three unused cores can be lowered to even 800MHz. The voltage needed normally is now diverted to the other cores. This allows dynamic overclocking to be achieved without exceeding the 125W thermal design power (TDP).

Phenom II X6 processor (Thuban architecture) die (258mm x 346mm). You can see the six cores clearly with the L2 cache in-between them. To the right you can spot the shared L3 cache. And all the way to the left you can spot the 128-bit memory controller.