The processors

Alder Lake - a Hybrid Computing Architecture

It hasn't exactly been a secret that Intel has been putting in significant effort to re-take the CPU market. After numerous respins, it was time for a new architecture, created from the ground up with a hybrid design; meet Alder Lake, which you've probably already heard a lot about. They will also be the first to adopt a hybrid architecture, similar to ARM's BIG.little, that combines high-performance cores combined with efficient ones, making them the first of their kind for Intel. Furthermore, this new generation is now proven to be the first to support DDR5 memory (DDR4 compatible memory controllers as well) and PCI-Express 5.0, making it the first generation to do so.

Alder Lake CPU architecture has two different CPU cores

The following are a set of slides from the presentation that you can view. As previously indicated, we acquired this information hours before the embargo was lifted and will fill in the gaps throughout the day. Mind you the Core i9-12900K has 16 cores and 24 threads. 8 P-Core (16 threads) and 8 E-Core (with 8 threads). The CPU has 30 MB L3 cache, 3 MB per core (Golden Cove) and 3 MB per cluster (E-Core) (Gracemont). That's 8 P-Cores for 24 MB and 6 MB from each of the two clusters of 4 E-Cores. The chip has 12.5 MB of L2 cache and 1.25 MB of L3 cache.

Gracemont (energy efficient cores)

Alder Lake is Intel's codename for the 12th-generation of Intel Core processors based on a hybrid architecture utilizing Golden Cove high-performance cores and Gracemont power-efficient cores. According to Intel, Alder Lake is a "performance hybrid" in their portfolio, as it is focused on performance rather than power consumption. Gracement, wasn't that Intel Atom related? Gracemont is an upcoming microarchitecture for low-power processors that will also be used in Intel's systems on a chip (SoCs). It will be the successor of the Tremont microarchitecture. Additionally, it will be deployed as low-power cores in a hybrid architecture for Intel's Alder Lake processors, similar to its predecessor.  The cores have been further enhanced. Gracemont is actually the 4th generation out-of-order low-power Atom microarchitecture, built on the Intel 7 manufacturing process. Intel also says that Alder Lake will provide the most performance per watt of any of its processors. You're going to notice a number of things, among them, increases in L1 caches; the Instructions cache for example was doubled to 64KB with an up to 4MB L2 cache, remember we're still talking the energy-friendly cores here. Microsoft will have to introduce support for these sophisticated scheduling features to x86-64 Windows in order for them to be supported for the next-generation hardware schedulers. Key changes:

• 64KB per core Level 1 instruction cache
• DDR5 memory
• PCIe 5.0 support
• Support for AVX, AVX2, and AVX-VNNI instructions

Alder Lake-S will include 8 Golden Cove cores and 8 Gracemont cores, according to Intel, who verified this during the company's architecture day. It will be manufactured utilizing Intel's Intel 7 technology, which was previously known as the Intel 10 nm Enhanced SuperFin process. As previously stated, Alder Lake-S will have 8 Golden Cove cores, which are high-performance cores, and 8 Gracemont cores, which are high-efficiency cores. Due to the fact that Gracemont cores do not support Hyper-Threading (HT), Alder Lake-S will only be able to provide 16 cores and 24 threads, which is the same as the i9-12900K configuration.

CPU

• Further information: Golden Cove (microarchitecture) and Gracemont (microarchitecture)
• Golden Cove high-performance CPU cores
• New instruction set extensions[6]
• Gracemont high-efficiency CPU cores
• Next-generation hardware scheduler; adding support for these advanced scheduling capabilities will require Microsoft to add support for them to x86-64 Windows.

GPU

• Intel Xe (Gen12.2) GPU

I/O

• New LGA 1700 socket[8]
• PCI Express 5.0
• DDR5 memory support for desktop CPUs
• LPDDR5 memory support for laptop CPUs
• DMI 4.0 x8 link with Intel 600 series PCH chipsets 

The integrated graphics is based on Xe, and it has up to 96 EUs for the GPU and 32 EUs for media functions only, according to the manufacturer. For a fully equipped processor, you'll receive eight performance cores as well as eight energy-efficient cores; the performance cores have SMT (hyper-threading), which means you'll end up with a total of 24 CPU threads. 

DDR5 Memory subsystem

The memory subsystem, which is DDR4 and DRR5 compatible, has a large amount of transistor real estate Intel clearly invested heavily in it. Intel continues to list memory at the JEDEC specification level, implying that it is unable to go any further. DDR4 memory operates at 3200 MHz, while DDR5 memory operates at 4800 MHz by default. You can already see that the memory bandwidth is likely to rise dramatically with DDR5 technology. So support at JEDEC defaults is Dual Channel PC5-38400U (DDR5-4800) or PC4-25600U (DDR4-3200). New and included in DDR5 is XMP 3.0, in total 5, but up to three manufacturer timing and frequency profiles can now be stored inside the DIMM. However, 2 remaining profiles can be configured and written by the end-user. meaning if you can find a sweet spot for your memory (frequency, timings, and voltage wise) you can store that profile to SPD. 

PCI Express 5.0

Alder Lake will enable PCI Express 5.0, which will more than double the bandwidth available from Gen 4, reaching a whopping 64 GB/s over 16 lanes, as predicted by rumors and now confirmed by Intel. Comparatively, PCIe Gen 3.0 (which is fast) can carry 16 GB/s across 16 lanes. Interconnects will be required to connect everything together. AMD refers to this as the infinity fabric, whereas Intel refers to it as the compute fabric; two distinct names for the same concept. The DMI interface between CPU and chipset also has received a massive upgrade to DMI 4.0, 16GT/s (PCIe 4.0 x8).

The Z690 chipset

Intriguing is the diagram for the Z690 chipset, which is the highest-end model released first. The CPU has 16 (or 2 times 8 PCIe 5.0 lanes), which can be used for graphics or storage, in addition to four NVME 4.0 lanes. What was previously said appears to be correct; the chipset has 12 times gen4 and 16 times gen3 processors. Additional features include support for two DIMMs per memory channel and dual-channel DDR4-3200 or DDR5-4800 with two DIMMs per memory channel.

• Supports both DDR4 and DDR5, with standard data rates of at least DDR5-4800 compliant on four-module configurations.
• Will automatically use Gear 2 or Gear 4 modes for DDR5, running the memory controller at ½ or ¼ speed, depending on data rate.
• Retains 20 CPU PCIe lanes, but 16 of those are increased to PCIe 5.0 data rates.
• Uses DMI 4.0 to connect the CPU to the PCH (chipset) at PCIe 4.0 x8 speeds.
• New PCH has four more PCIe lanes, including 12 PCIe 4.0 and 16 PCIe 3.0.
• Supports up to four USB 3.2 2×2 (20Gb/s) ports.
• New CNVio modules support Intel Wi-Fi 6E, and possibly Wi-Fi 7.
• Uses “Big-Bigger” hybrid cores to improve thread handling while retaining 125W TDP.
• Lower stack height requires new CPU cooler bracket.

 In order to improve performance, the Direct Media Interface link is being upgraded from DMI 3.0 x8 to PCIe 4.0. Additionally, there are 5 and 1 gigabit Ethernet, four USB 3.2 gen 2x2 ports, and WiFi 6E standards.