AMD Ryzen 3 3100 and 3300X processor review - Ryzen 3000 processor family

The Ryzen 3000 - Generation 3 (Matisse) processors

As you all know, ever since 2019 AMD has been making a series of announcements on its processor platform, several procs based on the Ryzen 3000 series, and that X570 chipset. We’ll first walk through all that became available in Q4 2019 to get you an idea of has been released and, of course, talk a bit more about the chiplet design and what that is all about. Meet the processors that are going to be injected into the market over the past months:

• 16-core Ryzen 9 3950X will be priced 749 USD
• 12-core Ryzen 9 3900X will be priced 499 USD
• 8-core Ryzen 7 3800X will be priced 399 USD
• 8-core Ryzen 7 3700X will be priced 329 USD
• 6-core Ryzen 5 3600X will be priced 249 USD
• 6-core Ryzen 5 3600 will be priced 199 USD
• 4-core Ryzen 3 3300X will be priced 120 USD
• 4-core Ryzen 3 3100 will be priced 99 USD

A slight difference between 3100 and 3300X

Today is all about the Ryzen 3 3100 and 3300X though, both have four cores and  threads. However, there are some subtle differences in-between the two new Ryzen 3 processors that you should not take lightly. First and foremost the CCX assignments are different. Each die used for any single die Ryzen 3000 processor still holds the very same 8-core die with two 4-core clusters, each labeled as CCX. 

The Ryzen 3 3100 will get a (2:2) configuration so from each CCX it will take two cores. The reality there is that makes it slower than the Ryzen 3300X that uses one full CCX (4:0). And that matters when we look at caches, specifically latency in relation to the 16 MB L3 caches. While both have 16 MB L3, the 3100 uses 8MB per CCX thus 2x8MB. The 3300X can utilize the full 1x16MB from a CCX, and fewer paths to follow means less latency means faster performance.  So that Ryzen 3  3300X has been dealt the better hand, one full CCX is activated this processor will benefit from that as well. Next to that, you have to add the clock frequencies into account as well. Other then these differentiations, it's all the same.  

• Ryzen 3 3100 3.6 MHz base and 3.9 Mhz Boost frequency
• Ryzen 3 3300X 3.8 MHz base and 4.3 MHz Boost frequency

Chiplet design

AMD has been moving towards a chiplet design starting with Ryzen 3000, aka ZEN2. Multi-die chips, thus multiple chips in one package is what we're talking about when we refer to a chiplet design, it’s one of the many answers to be able to fight off Moore's Law, now and in the future. AMD was already using the technology to connect multiple processors in Threadripper and, for servers, Epyc. Actually, also Intel with Kaby Lake-G. Chiplets, these are multiples of chips put together on an interposer that form the actual chip. Chiplets for AMD Ryzen 3000, Zen 2 feature an I/O die along with 7nm CPU chiplets (each holding eight cores per die). To be able to accomplish that, AMD has been updating its Infinity Fabric that connects the different dies that hold the cores. Current Epyc, Ryzen and Threadripper CPUs are all connected via the Infinity Fabric.

With the Zen 2 architecture, AMD places one I/O die chip that sits in the middle, which is connected to one or two 8-core dies. These AMD CPU chiplets are connected with 2nd generation Infinity Fabric (the interlink wires that connect them all). Why chiplet designs? One of the bigger issues at hand when manufacturing large monolithic CPU/GPU dies is that yields decrease nearly exponentially, and costs go up due to non-working dies. Multiple smaller chips in one package have higher yields, less loss and thus can be more profitable. 

Architecture

Zen 2 architecture is an advancement of Zen, and Zen had some bottlenecks that need to be dealt with. These are solved in this design and, at the same time, thanks to the smaller 7nm transistors, added extra functionality in important places. The image below shows the block diagram of the Zen 2 core. You will spot a new branch predictor, a larger micro-op cache, an additional address generation unit and a new floating point unit, which can handle 256-bits at the same time. 

You are going to notice some differences between the three cache levels. The L1 instruction cache has become smaller, the data cache is the same as last gen. The L2 cache is also the same, however the L3 cache was doubled up from last gen. AMD reduced the L1 instruction cache from 64 kB to 32 kB. The instruction cache contains the x86 instructions that are retrieved from the memory for processing. However, by giving this cache more inputs and outputs, 8-way associative instead of 4-way associative, it will make up for that design choice. Also, by optimizing algorithms for pre-fetching instructions and increasing the caches at other levels (like the L3 cache), the effect of the smaller instruction cache is limited. The L1 data cache was 32 kB in Zen and remains at 32 kB for Zen 2. Also unchanged is the L2 cache, which is still 512 kB per core. The L3 cache, however, is shared by the cores and that one has doubled up in size. Four cores are partitioned together in a group called a core complex (CCX). The earlier generation Zen processors had 8 MB of L3 cache, this has been doubled up to a whopping 16 MB of L3 cache. Why the double L3 cache? Well, AMD needed to address the latencies for accessing working memory to cope with the chiplet design, whereby the memory controller is physically located in a different chip, ergo a doubled L3 cache. Increasing any sort of cache is costly. It takes up a substantial portion of the available transistor budget, here is where 7nm helps out greatly.

Ryzen Gen 3 has also been fitted with an improved branch predictor that is now working according to a TAGE algorithm. Scientific studies are indicating that this model predictor offers the best results. Also, an important adjustment is to double the size of the micro-op cache to 4000 instructions. Substantial changes in the new design were also made to the floating point execution units, calculation units that basically do math processing like addition, subtraction, multiplication, division, square root, and bit-shifting. Zen supported 128-bit, Zen 2 makes a move towards 256-bit which brings us to support for AVX2 instructions, these can be processed in one single clock-cycle now. Zen2 does not yet support AVX512. Load/store units have been optimized by doubling bandwidth from 16 bytes per clock cycle to 32 bytes per clock cycle. L/S units transport data to and from the caches and, via that route, to and from the memory.