NAND flash memory might get too dense at 10nm
The adoption rate of Solid state disks is fast and they are getting faster and faster. To gain higher volume sizes the NAND ICs need to shrink and that could pose an issue in the near future. Shrinking the die sizes of flash memory increases the storage density and reduces the production cost, but one major issue is that each time you shrink to a smaller process node, the ability of flash cells to reliably hold data goes down because the number of electronics in a gate decreases as well.
The Register posted an interesting article to discuss the future of flash memory and reports that at present, 10nm NAND technology is impractical and sub-10nm impossible because such very small cells have major issues with bit-line loading, interference and leakage, leading to signal retention and reliability issues, for which there are no solutions.
To increase capacity, NAND flash memory makers will likely have to turn to 3D stacking, and afterwards the technology will likely be replaced by something new like phase-change memory (PCRAM), spin-transfer torque RAM (STT-RAM) or Resistive RAM (ReRAM).
These problems may make 10nm NAND technology impractical and sub-10nm impossible. Park suggests that 3D stacking, putting dies on on top of another, could be away out of this trap. He charts various approaches and identifies issues with each one, mentioning yield and retention as overall issues.
Park's conclusion is that new memory types are needed; a post-NAND era is beckoning with replacement memory technology offering DRAM-like speed and addressability and NAND non-volatility.
One implication of this is the effect on NAND fab owners foundry investment plans. Why spend $5bn plus and take five years to build a flash foundry when, in five years time, NAND is at the end of its life and a post-NAND technology is being developed, or even in production [via dv-hardware].
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