The fourth iteration of PCIe will arrive in about four years from now.
The statement was made by no other than the PCI SIG's chairman, Al Yanes. PCI SIG announced at the end of June that it formed an exploratory group for the Gen 4 of the PCI Express standard, comprising members from companies such as AMD, Hewlett-Packard, IBM and Intel.
These are conducting various simulations using chip, channel, packet and socket data and have determined that a throughput of at least 16 GT/s is feasible for PCIe Gen 4. The experts are expected to deliver a final report until the end of this year.
Right now, it seems that in order to achieve the high transfer speeds that are required by the fourth iteration of PCI Express, scientists will have to focus more on the board-level channels through which the signal passes and less on developing specialized chips.
As a result, PCI Express Gen 4 may be limited to distances about eight to 12 inches in length, compared to the maximum 20 inches that can be covered by PCIe Gen 3.
In addition to increasing the transfer speeds of the standard, scientist will also look into reducing the latencies of PCIe Gen 4 as well as into other aspects of the standards such as forward error correction, deeper pipelining and error reporting and control.
The PCI Express 3.0 specifications were released in November of last year, but the standard has yet to be used in any expansion cards.