The D silicon stepping in the 45-nanometer process will be code-named Hydra and is alleged to be AMD's true response to Intel's Nehalem CPU micro-architecture. This silicon stepping will introduce an L2 cache level of 1MB per core, which means that the upcoming processors will enjoy twice as much cache memory over the existing K10.5 silicon.

More than that, the new micro-architecture will also bring the much-hyped High-K metal gate technology that has been jointly developed by AMD and IBM using 45nm SOI (silicon-over-insulator) cores. The first 45-nanometer SOI cores, however, will be introduced earlier, in both Deneb and Propus chips. Hydra will also bring a huge, 6 MB L3 cache pool that will be shared among all the processor's cores. The new chip is expected to hit the market in at least eight-core configurations, although the company is likely to introduce them as eight-core native designs, rather than the recently unveiled MCM (Multi Chip Module).

As far as the brute computing performance is concerned, it is estimated that Hydra processors will be able to deliver stock core frequencies of over 3 GHz.

It is currently unknown whether it will be as overclockable as Intel's counterparts, but this is highly unlikely to happen, given AMD's conservative stance when it comes to tweaking its chips. Intel took the same approach with the Nehalems, and rumor has it that only the Bloomfield-based high-end offerings will be ale to go beyond the default clock speed.

The Hydra chips will arrive on the market in mid-2009 or even later and in the meantime, Intel's Nehalems will be the only high-end alternative.